Nvidia, Huawei and Intel are racing on AI chips. Memory, yield and power shortages may decide who actually wins.
In this update
- Beijing is reportedly set to approve Nvidia's H200 for a handful of Chinese firms, but the cap may land below 200,000 chips, less than half of what was requested.
- High-bandwidth memory, TSMC's CoWoS packaging, and the wafer contracts behind both are locked up years in advance, and a separate constraint, actual chip yield, shrinks real supply further before a single unit ships.
- DeepSeek's own R2 model is the clearest public evidence that Huawei's Ascend chips can run inference well, but still cannot reliably finish a frontier training run, and rack-level power density has now become a second bottleneck even after a data center clears its grid connection.
Nvidia leads on raw performance, Huawei has closed the gap on inference, and Intel is chasing a cheaper inference lane. None of the 3 controls the actual ceiling on how much AI hardware reaches the market in 2026. That ceiling comes from HBM memory and TSMC packaging capacity sold out into 2027, wafer supply locked up years ahead through prepaid contracts, a chip yield gap on China's domestic node, cluster designs that punish mixed GPU generations, and a US grid and rack power problem that outlasts a fully funded data center. This piece is built for anyone who needs the practical picture rather than a press-release version: investors tracking semiconductor exposure, builders deciding which chip ecosystem to commit to, and policy or business readers who want to know which claims in this race actually hold up before repeating them. Read it in one sitting for the full picture, or jump to any section for a fast, sourced answer on that specific piece of the story.
Every big AI story eventually comes back to one thing: the physical chip that runs the math. Chatbots, self-driving software, and drug discovery models do not work without AI chips. In 2026, the fight over who makes them, who buys them, and who gets banned from buying them has become one of the biggest business and political stories of the year.
This piece breaks down what AI chips are, why Nvidia still leads the pack, why Huawei is closing the gap faster than most people expected, and why Intel keeps showing up to a fight it has not yet won. It also goes beyond the headlines into parts of this story that rarely get covered: the yield problem behind every Huawei production number, why one flagship chip design ends up shipping as several different products, the wafer contracts that lock in supply years before a chip ships, the physics that separates Nvidia's and Huawei's opposing hardware bets, why mixing chip generations inside one cluster can backfire, the power problem that starts only after a data center clears its grid queue, and the allocation politics that decide who gets supply first. No hype, no guesses about the future, just what is happening right now, with sources.
A quick note on tone before we get into it. This market moves fast enough that a headline from March can look outdated by June, and much of the coverage treats every product announcement like it has already shipped. We are sticking to what companies have confirmed, what analysts have independently verified, and what executives have said on the record. If a number looks impressive, we will tell you whose number it is and how far it has been tested.
What is an AI chip, in plain terms
An AI chip is a processor built to handle the specific kind of math that machine learning needs: huge batches of matrix multiplication, done in parallel, over and over. Regular CPUs can do this math too, but they do it one step at a time. AI chips do thousands of steps at once, which is why training a model on a CPU can take months while the same job on the right AI chip takes days.
Most AI chips fall into two jobs. Training chips build the model, feeding it enormous datasets so it learns patterns. Inference chips run the finished model, answering a prompt or recommending a video. Training needs raw power. Inference needs speed and a low cost per query, since a company might run billions of queries a day. The AI models that actually use this hardware, including systems like Anthropic's newer Claude models, are themselves shaped by which chips their training runs land on.
NVIDIA's GPUs dominate training. Intel, AMD and a handful of Chinese firms are trying to carve out space in the inference market instead, because inference is cheaper to build for and the market keeps growing as more companies deploy AI instead of just testing it.
Size matters here too. A modern AI chip is not one small piece of silicon. NVIDIA's Blackwell and Vera Rubin chips are built from multiple chiplets fused together, wrapped in cooling systems that can weigh more than the server rack around them. Huawei gets around its manufacturing limits the opposite way, linking thousands of smaller chips together with fast interconnects so the total system output competes even when the single chip does not. Both approaches solve the same problem from different directions, and which one wins probably depends more on cost per query than on any single benchmark.
Why AI chip news will not slow down this year
Three things are colliding at once. First, the AI accelerator market itself has become enormous. NVIDIA's own fiscal 2026 results show data center revenue of 193.7 billion dollars for the year ended January 25, 2026, up 68 percent from the year before, out of total revenue of 215.9 billion dollars. That is not a niche industry anymore. That is one of the largest revenue lines in global technology, and the growth kept going: in the quarter ended April 26, 2026, Nvidia's data center revenue reached 75.2 billion dollars on its own, up 92 percent year over year, according to the company's first quarter filing.
Second, the US and China are locked in an export control fight that keeps changing week to week. Washington restricts what Nvidia and AMD can sell to China, then loosens the rules, then Beijing adds its own roadblocks on the other end. The restrictions started under President Biden in 2022 and were expanded by President Trump in 2025, before parts were reversed, allowing Nvidia to sell its H200 chip and AMD to sell its MI308 chip to China as of May 2026.
Third, China is no longer just buying chips. It is building its own, and the results are good enough to matter for at least one job in the AI pipeline. That is the part of this story that gets the least attention, and it is probably the most important one.
NVIDIA AI chips: still the biggest name, still the biggest target
NVIDIA's market share in AI accelerator GPUs sits at roughly 85 to 90 percent globally. For context, that is a level of dominance most industries never see from a single company. CEO Jensen Huang built this lead on two things: raw chip performance and CUDA, the software layer that lets developers use Nvidia hardware without starting from scratch every time.
The current flagship architecture is Vera Rubin, announced at CES 2026. It is built on TSMC's N3P 3-nanometer process with HBM4 memory and 336 billion transistors, and Nvidia says it cuts inference token generation costs by 10 times and reduces the GPU count needed for training mixture-of-experts models by 4 times compared to Blackwell, the generation before it. Those are Nvidia's own numbers, so treat them as a ceiling rather than a guarantee, but the direction is clear: each generation is meant to make AI cheaper to run, not just faster.
Here is the part that should worry Nvidia more than any single competitor chip: the China problem. Before export controls tightened, Nvidia held almost 95 percent of the advanced AI chip market in China, and the country made up about 13 percent of Nvidia's total revenue. That business has mostly evaporated, and Huang has said as much plainly in interviews.
NVIDIA vs. Huawei AI chips: the fight nobody thought Huawei could win this fast
In May 2026, Huang told CNBC that Nvidia has effectively given up on competing for China's advanced AI chip market against Huawei, even in the same stretch where Nvidia reported a quarter with revenue up 85 percent to 81.6 billion dollars, according to its first quarter fiscal 2027 results. A company can be printing money globally and still admit it lost an entire country to a rival that barely existed in this market 5 years ago.
Huawei's answer to Nvidia is the Ascend line, built through its HiSilicon chip division. The current workhorse is the Ascend 910C, and Huawei is not being shy about scaling it up. According to Bloomberg reporting cited by RCR Wireless, the company plans to produce around 600,000 Ascend 910C units in 2026, nearly double the prior year's output, with total Ascend family production reaching up to 1.6 million dies once older models are included. That figure is not the only one in circulation, and the gap between estimates is itself informative. SemiAnalysis's own production model, constrained specifically by how much domestic HBM memory is actually available rather than by logic-die capacity, puts realistic 2026 Ascend 910C output closer to 300,000 units, versus roughly 805,000 combined Ascend dies produced the prior year, according to its Huawei Ascend production ramp research note. The 600,000-unit Bloomberg figure and SemiAnalysis's roughly 300,000-unit HBM-constrained estimate are not the same claim answering the same question. One describes what Huawei intends to build. The other describes what its domestic memory supply can actually support once the HBM shortage covered later in this piece is factored in, and it is worth reading both before repeating either as settled fact.
On raw performance, Huawei is still behind. The 910C is built on SMIC's enhanced 7-nanometer process, compared to the 4-nanometer TSMC node Nvidia uses for its B200, and delivers roughly one-third the BF16 throughput of Nvidia's B200. Huawei's answer to that gap is not a better single chip. It is more chips wired together. The newer Ascend 950PR entered mass production using SMIC's N+3 process, a 5-nanometer-class node, and packs 1.56 petaflops of FP4 compute, 112 GB of domestically made HBM memory, and a 2-terabyte-per-second interconnect into a single chip at a 600-watt envelope. That is a real jump from the 910 generation, and it happened faster than most Western analysts expected.
The revenue numbers back up the shift. Huawei's own order book puts its 2026 AI chip revenue at approximately 12 billion dollars, up from 7.5 billion dollars in 2025, a jump of at least 60 percent, based on confirmed orders from Alibaba, ByteDance and Tencent, according to the Financial Times reporting carried by Tom's Hardware. Reuters has said it could not independently verify that figure, so it should be read as Huawei's own order-based projection rather than an audited result. On market share, TrendForce's own tracking, presented at its Shenzhen conference on June 24, 2026, put Huawei and Cambricon combined at 56 percent of China's AI server chip market in 2026, up from 46 percent in 2025, with Chinese in-house ASIC designs adding another 23 percent and Nvidia and AMD's combined share falling to 21 percent from 34 percent, according to TrendForce data reported by Nation Press. A separate DigiTimes report from August 12, 2026 put China's high-end AI chip market at nearly 90 percent domestic by sales, leaving Nvidia, AMD and other foreign suppliers with roughly 10 percent, according to DigiTimes' own tracking. The 2 figures differ because they measure different things, AI server chips broadly versus the high-end segment specifically, and both point in the same direction: domestic supply has become the majority of China's AI chip market in 2026, not a growing minority of it. Behind Huawei, smaller Chinese players like Cambricon, Moore Threads and MetaX are grabbing whatever share is left. Morgan Stanley estimates China's domestic AI chip market could reach 67 billion dollars by 2030, according to the same Tom's Hardware report cited above, while TrendForce separately projected in December 2025 that China's high-end AI chip market would grow more than 60 percent in 2026 alone.
The yield problem hiding behind every chip production number.r
A production target and a count of finished, sellable chips are not the same number, and the gap between them is one of the least reported parts of this entire story. It comes down to yield: the share of dies cut from a single wafer that actually work once tested. A bigger die catches more manufacturing defects, and the Ascend line sits close to the physical size limit a single lithography pass can print, which makes yield unusually hard to hold high.
SMIC manufactures the Ascend chips on its 7-nanometer-class N+2 process, and the yield numbers reported for that line have moved a lot in a short time. Reports from Reuters, Yahoo Finance, and TrendForce in September 2024 put the Ascend 910C's yield at around 20 percent, while the older Ascend 910B on the same node reached about 50 percent. By early 2025, DigiTimes reported, citing the Financial Times, that 910C yield had climbed to nearly 40 percent, enough to make the production line profitable for the first time. As of April 2026, industry analysis still places 910C yield in the 20 to 40 percent range, well below a mature node, and describes the line as dependent on state subsidy to stay commercially viable.
| Chip | Fab process | Reported yield | What changed |
|---|---|---|---|
| Ascend 910B | SMIC 7nm (N+2) | About 50 percent (2024 reporting) | Older, more mature run on the same node |
| Ascend 910C | SMIC 7nm (N+2) | About 20 percent (September 2024), near 40 percent (early 2025) | Yield roughly doubled within months, enough to turn the line profitable |
| Ascend 910C | SMIC 7nm (N+2) | 20 to 40 percent (reported as of April 2026) | Still described as reliant on state subsidy to remain commercially viable |
Figure: reported Ascend chip yield over time, based on Reuters, Yahoo Finance, TrendForce, and Financial Times reporting compiled by DigiTimes and industry analysis. Figures are analyst estimates and should be read as directional rather than exact.
The cause traces back to tooling rather than chip design. Export controls have kept SMIC off ASML's EUV lithography machines, so the company relies on multiple passes of older deep ultraviolet equipment to print features that EUV would normally handle in one pass. Each extra pass adds another chance for a defect or a misalignment, and that risk compounds on a die as large as the Ascend's.
Translate that into a supply forecast and the picture changes. SemiAnalysis puts SMIC's total advanced node capacity, 7 nanometer and below, at approximately 45,000 wafers a month by the end of 2025, climbing to 60,000 in 2026 and 80,000 in 2027, according to its Huawei Ascend production ramp research note. At a 30 to 40 percent yield, a wafer-start plan and a shipped, sellable chip count are 2 different figures, and the gap between them is exactly why a headline production target reads better as a ceiling than as a delivery promise.
None of this makes Huawei's progress fake. The 910C's climb from 20 percent to nearly 40 percent yield in under a year is a genuine engineering achievement on a node built without EUV tools. It does mean that any comparison between Nvidia's and Huawei's chip output needs to account for yield, not just wafer starts, because the same manufacturing capacity produces a very different number of usable chips depending on how mature the process behind it actually is.
Why one flagship chip design ends up shipping as several different products
A chip's name on a keynote slide rarely tells you which physical part actually reaches a customer, and this is one of the most misunderstood parts of chip supply. Two separate mechanisms cause it, and articles covering this market rarely separate them.
The first is manufacturing reality. Every wafer that comes off a lithography line carries dies with small, scattered defects, and instead of scrapping every flawed die, foundries test each one and sort it by what still works. This process, called binning, is standard across the chip industry and is not unique to any single company. A die with a defect in one memory block can still ship as a lower-tier product instead of getting thrown out, which is part of why a single production run can quietly become several different SKUs at several different price points.
The second mechanism is policy-driven rather than manufacturing-driven, and it shows up clearly in Nvidia's China-specific chip history. After the first round of US export controls in 2022, Nvidia built the H800 by cutting the H100's chip-to-chip interconnect bandwidth to roughly half of the original, down to around 300 to 400 gigabytes per second from about 900, enough of a downgrade to fall under the restriction threshold while keeping most of the core compute intact, according to Tom's Hardware's reporting on the original restriction. When Washington tightened the rules again in October 2023, the H800 got banned too, and Nvidia built the H20 as a further stripped-down Hopper variant instead, later modifying it again in 2025 after another rule change, according to Introl's export control tracker.
| Chip | Base design | What was changed | Why |
|---|---|---|---|
| A800 | A100 | NVLink bandwidth cut from 600 to 400 GB/s | 2022 export threshold, later banned outright in 2023 |
| H800 | H100 | Interconnect bandwidth cut to roughly 300 to 400 GB/s from about 900 | 2023 export threshold, later banned outright |
| H20 | Hopper | Compute and memory capability deliberately reduced below H100 levels | Built to stay inside the 2025 AI Diffusion Rule's approved zone, then modified again after further rule changes |
Practical takeaway: whether the downgrade comes from a manufacturing defect or an export rule, the result for a buyer is the same. The chip announced on a keynote stage, and the chip that actually ships to a given customer or region are not always the same part, and reading only the flagship name in a headline can miss which variant is realistically available. DeepSeek's own R1 model was reportedly trained using large volumes of the export-compliant H800, well below Nvidia's top-tier chip, which is itself evidence that a downgraded variant can still produce a near-frontier result in the right hands.
HBM memory and TSMC's packaging capacity cap how many AI chips reach the market in 2026
Chip supply is not just a function of how many wafers TSMC can produce. High bandwidth memory, known as HBM, and TSMC's CoWoS advanced packaging process, which fuses that memory onto the chip, decide who can actually ship hardware in 2026. Neither sits fully inside any single chipmaker's control, and both are sold out well past this year.
TSMC's own CEO, C.C. Wei, told shareholders at the company's June 2026 annual meeting that CoWoS capacity remains extremely tight and sold out through 2026. Multiple analyst estimates, including figures reported by DigiTimes and cited across Tom's Hardware and Morgan Stanley research notes, put Nvidia's booked share of TSMC's 2026 CoWoS capacity at roughly 800,000 to 850,000 wafers, close to 60 percent of the total. That allocation covers current Blackwell Ultra production and reserves capacity for the incoming Rubin architecture at the same time, which leaves a shrinking slice for everyone else, including Broadcom, AMD, and Google's custom TPU chips. Google reportedly had to cut its 2026 TPU production target from about 4 million to 3 million units for exactly this reason.
Huawei's version of this problem is HBM itself rather than packaging. The SemiAnalysis newsletter estimates that Chinese firms had stockpiled roughly 13 million HBM stacks from Samsung before export controls tightened, enough to support Ascend production through 2024 and 2025. The same research puts CXMT's 2026 HBM output at approximately 2 million stacks, which SemiAnalysis calculates is enough for only 250,000 to 300,000 Ascend 910C equivalent packages, a hard ceiling that holds regardless of how much logic-die capacity SMIC has available. That is the real reason Huawei's roadmap leans so heavily on linking more chips together rather than making each chip carry more memory. It has less domestic HBM to work with, not less silicon capacity.
Figure 1: estimated share of TSMC's 2026 CoWoS advanced packaging capacity by customer, based on DigiTimes and Morgan Stanley figures reported by Tom's Hardware and industry trackers. Figures are analyst estimates, not company disclosures, and should be read as directional rather than exact.
The wafer contracts that lock in chip supply years before a launch event
Long before a chip reaches a keynote stage, its supply is already decided through contracts that almost no consumer tech coverage explains. TSMC's 2024 annual report, filed with the US Securities and Exchange Commission as a Form 20-F, disclosed that customers collectively prepaid the company roughly 291.1 billion Taiwanese dollars, close to 9 billion US dollars, to secure multi-year capacity allocations, according to analysis of TSMC's SEC filings published on Medium. Nvidia's own financial disclosures confirm the same pattern from the buyer's side: the company has stated it placed non-cancellable inventory orders, paid premiums, and provided deposits specifically to secure future supply and capacity, according to Tom's Hardware's coverage of TSMC's prepayment disclosures.
This is not a niche accounting detail. It is the mechanism that decides who gets capacity before a chip design is even finished, and a real filed contract from a much smaller chip company shows exactly how the terms work. Cirrus Logic's 2021 Capacity Reservation and Wafer Supply Commitment Agreement with GlobalFoundries, disclosed in its own SEC filing, required the company to pay a 50 million dollar non-refundable capacity reservation fee, prepay an additional 175 million dollars toward future wafer purchases, and commit to buying at least approximately 1.6 billion dollars of wafers over the 2022 to 2026 commitment period, with shortfall payments due if it failed to purchase the agreed volume. That is what a take-or-pay wafer contract actually looks like in writing: the buyer pays whether or not it ends up needing every wafer it reserved.
Not every customer gets the same deal. According to SemiAnalysis reporting on TSMC's wafer supply agreements, Apple has historically avoided prepayment obligations entirely and can shift its committed capacity up or down across the year without the penalty structure smaller or newer customers face, a privilege that reflects its status as TSMC's largest and longest-standing customer rather than a standard industry term. That gap in bargaining power is the part of the allocation story that a simple capacity chart cannot show: 2 companies booking the same node can be operating under completely different financial exposure, and the company with the weaker contract terms is also usually the one with the least room to absorb a shortfall payment if its own AI roadmap slips.
Why this matters for reading production headlines: a booked wafer allocation, a signed take-or-pay contract, and a delivered, tested, sellable chip are 3 different things. A company can have committed billions of dollars to secure capacity and still end up with a smaller usable chip count than the contract implies, once the yield gap covered earlier in this piece is factored in. Overbooking out of fear of missing supply is a rational response to this contract structure, and it is also part of why real availability across the industry tends to run tighter than any single company's announced capacity would suggest.
NVIDIA AI chip demand China deal: what is actually being sold, and what is not
This is the part of the story that confuses people, because headlines make it sound like a done deal when it is closer to a stalemate. In mid-2026, the US Commerce Department cleared around 10 Chinese companies, including Alibaba, Tencent, ByteDance and JD.com, to buy Nvidia's H200 chip, with a cap of 75,000 units per customer, and licensed Lenovo and Foxconn as distributors.
That looked resolved on paper. It was not resolved in practice. As of mid-May 2026, not a single H200 chip had actually been delivered to China, according to Reuters reporting picked up by Yahoo Finance, despite the US approvals, because the deal remained stuck between American export rules and Chinese supply chain scrutiny. As of this update, the picture has shifted again, but is still not resolved. According to a TrendForce report from July 9, 2026, citing Reuters and The Information, Beijing appears ready to finally allow a limited group of AI companies, including Alibaba, ByteDance and DeepSeek, to acquire H200 chips, but the approved volume may land below 200,000 units, less than half of what Chinese buyers reportedly requested.
Why would China slow-walk its own companies from buying chips they are allowed to buy? Beijing is actively pushing its tech firms toward domestic suppliers like Huawei, and every H200 that gets approved is one less reason for a Chinese cloud company to keep investing in the Ascend ecosystem. This has become less a technology problem now, and more a policy negotiation, and Nvidia is stuck in the middle of it.
Even without China, Nvidia is not exactly struggling. The company's own fiscal first-quarter commentary noted that no shipments of Hopper-series data center products to China occurred during the quarter at all, compared with 4.6 billion dollars in the same quarter a year earlier, and revenue still hit a record. Huang still thinks the country matters long term, telling investors he expects the new CPU market driven by agentic AI systems to be worth 200 billion dollars, with China included in that estimate.
Ascend vs Nvidia: the workload question that decides the answer, not the marketing
Most coverage treats Huawei catching up as one universal claim. That is the wrong way to think about it. The honest answer depends entirely on what job the chip is doing, and the clearest public evidence of that split comes from DeepSeek, the Chinese AI lab behind the R1 model.
According to Financial Times reporting carried by Tom's Hardware, Chinese authorities encouraged DeepSeek to train its follow-up R2 model on Huawei's Ascend chips after the success of R1. DeepSeek tried. The training runs hit unstable performance, slower chip-to-chip connectivity, and limits in Huawei's CANN software toolkit, and even after Huawei sent its own engineers on site, the team could not complete a successful full training run on Ascend hardware. DeepSeek switched back to Nvidia chips for training and kept Ascend for the inference side of the model instead, and the delay pushed R2's launch back by months.
That single case study says a lot about the wider market. Here is a rough breakdown of where the evidence points, drawn from the DeepSeek episode, along with public specs and vendor claims:
| Workload | Where Ascend stands today | Deciding factor |
|---|---|---|
| Inference on an already trained model | Viable, and Huawei's main current strength | CANN software is mature enough for serving; the interconnect scale compensates for the lower per-chip throughput |
| Training a frontier model from scratch | Not yet reliable at scale, per DeepSeek's own experience | CANN and driver stability at large cluster sizes, plus no native FP8 support |
| Fine-tuning or reinforcement learning on an existing model | Mixed, workload dependent | Smaller cluster sizes reduce exposure to interconnect and stability issues seen in full pretraining |
| Latency-sensitive, high-concurrency serving | Competitive for many Chinese domestic deployments | Cost and availability inside China often outweigh the raw throughput gap versus Nvidia |
The takeaway is that Huawei has closed the gap for one job, inference, and China has decided that is enough for now, while it keeps working on the harder problem of training.
Why a stable chip in testing can still fail at full cluster scale
DeepSeek's stalled Ascend training run raises an obvious question. If the chip performs well enough for inference, why would it struggle so much with training the same underlying model? Part of the answer has nothing to do with Huawei specifically. Running any chip across a cluster of thousands of units for weeks at a time exposes failure modes that never show up in a small test.
Meta's own published research on training Llama 3's 405 billion parameter model makes the point clearly, using Nvidia's mature, market-leading hardware and software stack. Over 54 days on a cluster of 16,384 H100 GPUs, the run hit 419 unexpected component failures, an average of one every 3 hours. GPU issues, including NVLink faults, caused 148 of those failures, and the GPUs' onboard HBM3 memory caused another 72, together accounting for roughly half of every interruption on the run.
That is Nvidia's own flagship stack, not an underdog's. It shows that hardware failure at this scale sits closer to a law of large numbers than a defect. What separates a smooth training run from a stalled one is whether the software around the hardware, fault detection, checkpoint and restart routines, and the collective communication library that keeps thousands of chips synchronized, can recover from a failure in seconds instead of losing hours of progress.
Nvidia's NCCL communication library has had roughly a decade of production hardening across exactly this kind of large-scale run. Huawei's equivalent, along with its CANN software toolkit, is newer and has not been tested at frontier training scale nearly as often. Read against that backdrop, DeepSeek's reported instability, connectivity issues and toolkit limits while training its R2 model on Ascend hardware point toward a fault recovery stack meeting frontier scale demands for the first time. That is a software maturity gap, not necessarily a fixed ceiling on the silicon itself. The distinction matters for reading Huawei's next attempt: a software problem can be fixed with the next CANN release, while a hardware ceiling could not.
Intel Nvidia AI chip competition: the underdog story that is not over yet
Intel spent years watching Nvidia and AMD take over the AI chip market while its own attempts, like the Gaudi series, landed with a thud. In 2026, Intel is trying again, and the plan looks more grounded than flashy.
The centerpiece is Crescent Island, an inference-focused data center GPU that Intel first showed at the OCP Global Summit in October 2025 and detailed further at Computex 2026. The interesting part is the memory choice. Instead of the expensive HBM that Nvidia and AMD use, Crescent Island's reference design runs on 160 GB of LPDDR5X, the kind of memory more commonly found in laptops and phones, according to Intel's own announcement. At Computex, Intel confirmed board partners will have the flexibility to build variants with up to 480 GB of that same memory, and the chip carries a 350-watt power target aimed at air-cooled enterprise servers, per TechSpot's coverage of the announcement. Customer sampling is scheduled for the second half of 2026, with general availability expected in 2027.
That is a deliberate cost decision aimed at cutting the price per query for a large share of everyday inference work, not a corner cut by accident. Intel is betting that cheaper memory in air-cooled server racks beats expensive HBM in liquid-cooled ones, for that same slice of the market. Intel CTO Sachin Katti has framed the strategy around a shift from static training toward constant, everywhere inference driven by agentic AI, arguing that this calls for systems that pair the right silicon with the right task rather than one chip trying to do everything. Intel is not trying to beat Nvidia at the training game Nvidia already won. It wants the cheaper, high-volume inference lane instead.
The business numbers give Intel some room to try. Intel's data center and AI segment posted 5.1 billion dollars in revenue in the first quarter of 2026, up 22 percent year over year, and Intel's stock had surged more than 200 percent year to date by mid-2026. Some of that comes from a broader manufacturing comeback story, not just AI chips. Intel secured more than 18 billion dollars in fresh funding, including 11.1 billion dollars from the US government, 5 billion dollars from Nvidia itself, and 2 billion dollars from SoftBank. Nvidia is funding a company that is trying to compete with it, a detail that says something about how tangled these business rivalries have become. The funding also lands inside a wider push by Washington to rebuild domestic chip manufacturing, a theme that shows up elsewhere in US tech policy this year, including in how politically branded tech ventures have leaned on similar buy-American messaging.
Intel's other angle is its own foundry business. Panther Lake, its first laptop chip built on the new 18A manufacturing process, is already shipping in more than 200 laptop designs and delivers 180 total platform TOPS, though that figure combines the CPU, GPU and NPU together rather than measuring one component alone. Clearwater Forest, Intel's first 18A server chip, launched in the first half of 2026 with up to 288 cores. Every one of these products is also a pitch to outside customers: if Intel can manufacture its own chips well on 18A, it can convince other companies to let Intel manufacture their chips too.
Will Intel actually dent Nvidia's inference lead? Too early to say. Crescent Island has not shipped to a single paying customer yet, and Intel has not published raw throughput numbers for the chip. Sampling later this year will tell us more than any press release has so far.
Why a chip's spec sheet number and its real-world number are rarely the same
This is the section almost every consumer-facing chip article skips, and it is one of the most useful things to understand before comparing any two chips by their advertised numbers. Engineers who train large models track a metric called model FLOPs utilization, or MFU: the share of a chip's theoretical peak compute that a real training or inference job actually achieves once memory bandwidth limits, chip-to-chip communication overhead and software scheduling are factored in.
Meta's own published research on Llama 3.1 reported an MFU of 38 to 43 percent during training, and separate industry benchmarking generally puts well-optimized dense model training in the 40 to 55 percent range on Nvidia's mature CUDA stack, with mixture of experts training often landing lower, around 25 to 40 percent, because sparse routing fragments compute across the cluster. Inference has its own ceiling: prefill stages often reach 30 to 50 percent MFU, while decode stages can sit in the single digits by design, since decode is limited by memory bandwidth rather than raw compute.
Why this matters for a buyer: a chip with a higher peak FLOPS number on paper can still lose in practice if a competing chip's software stack is mature enough to capture a larger share of that peak. CUDA has had over a decade of kernel-level optimization work behind it. Huawei's CANN toolkit and AMD's ROCm are newer and generally show a wider gap between advertised peak and real achieved throughput, which is part of why DeepSeek's training runs on Ascend hardware ran into instability that a comparable Nvidia cluster would not have hit as often. Comparing 2 AI chips by peak TFLOPS alone, without asking how much of that peak a real workload can capture, is the single most common mistake in casual chip coverage.
Scale up or scale out: the physics limit behind Nvidia's and Huawei's opposing bets
Every AI chip discussed so far runs into the same physical ceiling before any comparison of specs even starts. A standard lithography reticle, the template a chip gets printed from, caps a single die at 858 square millimeters, a 26 by 33 millimeter rectangle set by the scanning tool's range. Nvidia's B200, Huawei's Ascend and AMD's MI300 series are all multi-die packages for exactly this reason. No single die fits what a modern AI accelerator needs inside one reticle.
TSMC's advanced packaging technology, CoWoS, is what lets a design go beyond that limit by fusing several dies and memory stacks onto one interposer. The current version, CoWoS-S, tops out around 3.3 times reticle size, about 2,831 square millimeters, and is the technology behind the H100, the B200 and AMD's MI300X. CoWoS-L, due for production in 2026, pushes that to roughly 5.5 times reticle size, about 4,719 square millimeters. TSMC's published roadmap goes further still: a 9.5 times reticle interposer carrying 12 HBM5 stacks by 2027, and packages beyond 14 times reticle size, more than 12,000 square millimeters, with up to 24 HBM5E stacks by 2029. Packaging, not lithography, is now the actual scaling frontier for AI chips.
That escalation runs into its own physical limit. A silicon interposer is only about 100 microns thick, roughly the width of a human hair, and grows more fragile as it scales toward the larger reticle multiples, with a real risk of cracking or delaminating during manufacturing. Nvidia's scale-up approach, packing more compute and memory into an increasingly large single package, is a bet that packaging engineering keeps outrunning that fragility limit.
Huawei's Ascend architecture takes the opposite bet. Rather than pushing one package past the fragility limit, it links many smaller, weaker chips together over a fast interconnect and lets the total system make up for what any single chip lacks. That approach avoids the interposer's physical ceiling, but it pays a different cost: as the chip count in a cluster grows, a larger share of total power and time goes into moving data between chips instead of computing on it. For workloads that need constant synchronization across every chip in a cluster, dense pretraining chief among them, that communication overhead grows faster than the cluster itself. For workloads that split cleanly across chips with limited cross-chip chatter, inference chief among them, the same overhead barely registers.
| Approach | What it optimizes | What limits it | Workload it favors |
|---|---|---|---|
| Scale up (Nvidia) | Compute and memory density inside one package | Interposer fragility as reticle multiples climb | Dense, tightly synchronized training |
| Scale out (Huawei) | Avoiding the interposer fragility ceiling entirely | Communication overhead that grows with chip count | Inference and workloads with limited cross-chip chatter |
That is the physical reason behind the exact split in Huawei's chip strategy already covered above: workable for inference, still unreliable for full frontier pretraining. It also sets up the more interesting long-term question. Whichever limit gives way first through engineering, interposer fragility on Nvidia's side of the bet or the communication tax on Huawei's, will likely shape the next generation of AI chips more than any single product launch this year.
When chasing the newest chip actually slows a cluster down
Standard advice in this market says buy the newest, fastest chip available. That holds for a single machine. It stops holding the moment a company adds new chips into a cluster that is already running an older generation, and the mechanism behind that is simple once you see it.
Most production training runs use synchronous updates, because they produce stable, predictable convergence. In a synchronous cluster, every chip has to finish its step before any of them can move to the next one, which means the slowest chip in the room sets the pace for every other chip in it. One engineering team running production AI systems tested this directly by mixing Nvidia B200 and A100 GPUs inside the same training job. The A100s finished their forward pass about 30 percent slower than the B200s, and the newer B200s then sat idle roughly 30 percent of the time waiting for the older chips to catch up, according to awrite-upp published by the team behind the test. Total throughput dropped by more than the raw percentage of slow chips in the mix would suggest, because synchronization overhead compounds on top of the underlying speed gap. Separate technical guidance on multi-GPU training reaches the same conclusion in general terms: mixing GPU types creates a performance ceiling set by the slowest card in the cluster, and teams that must mix hardware are usually better off pairing similar architectures rather than combining dramatically different generations.
The upgrade decision is rarely just about the new chip's price either. Moving a cluster to a new chip generation usually means retraining engineering teams on a new toolkit version, re-validating checkpoint and fault-recovery routines against the new hardware, and re-tuning how the model gets split across chips, all real costs that a spec sheet comparison leaves out. A company already running a large, proven cluster on one chip generation can end up better off buying more of that same chip than buying a smaller number of the newest one, simply because total, reliable throughput across a homogeneous cluster beats a mixed cluster's peak spec on paper.
When this doesn't apply: the trap is specific to tightly synchronized training. Inference workloads that split cleanly across chips with little cross-chip communication, and asynchronous or loosely coupled jobs, tolerate hardware mixing far better, which is one more reason chip strategy has to be matched to the specific workload rather than treated as one universal buying decision.
Other AI chip companies and AI chip makers worth knowing
NVIDIA, Huawei and Intel get the headlines, but the list of serious AI chip makers is longer than that, especially inside China, where export restrictions forced an entire domestic industry into existence almost overnight. This is one of the odder side effects of the export control fight. The US intended to slow China down. Instead, it created guaranteed demand for half a dozen Chinese chip startups that might not have survived a fully open market where Nvidia could sell its best hardware to anyone who wanted it.
AMD remains Nvidia's closest Western rival, with its Instinct line competing directly in data center training and inference. Alibaba's chip division, T-Head, has quietly become a real commercial player, with cumulative AI chip shipments now exceeding 470,000 units, more than 60 percent of which go to external commercial customers outside Alibaba itself, spanning manufacturing, automotive and finance.
Baidu's Kunlunxin division is another one to watch. Its third-generation P800 chip runs on a 7-nanometer process and delivers 345 TFLOPS of FP16 performance, benchmarked against Nvidia's older A100 and Huawei's Ascend 910B. Hygon, which builds both CPUs and AI accelerators, posted first-quarter 2026 revenue of 4.034 billion yuan, up 68 percent year over year, with a next-generation chip aimed at matching H100-class performance later this year.
None of these companies threatens Nvidia's global lead today. Together, they represent a parallel AI hardware ecosystem growing inside China, built specifically because Nvidia's best chips are not available there. That is a structural shift in how the global AI chip supply chain works, one that connects to the broader story of infrastructure most people never think about until it breaks or gets rationed.
Outside China, the field looks different. AMD's Instinct MI400 series and its Helios rack systems, both shown at CES 2026, target the same hyperscale customers Nvidia serves: Microsoft, Meta, Amazon and Google. Qualcomm has pushed further into laptop chips with AI acceleration built in rather than added afterward, chasing the same Copilot Plus PC certification that Intel's Panther Lake already meets. Cerebras keeps building wafer-scale chips, a genuinely different physical approach where one giant piece of silicon, built through field stitching rather than conventional packaging, replaces dozens of smaller GPUs wired together, taking the scale-up bet described above to its most extreme form. None of these companies will unseat Nvidia this year. Each one chips away at a slightly different corner of the market, and those smaller corners add up over time.
Chip allocation politics: who actually gets Nvidia's supply first
This is the layer of the story that decides who can actually build with this hardware, and it has almost nothing to do with which chip is objectively best. NVIDIA's supply is not sold on a first-come basis. Hyperscalers, including Microsoft, Amazon, Google and Meta, signed multi-billion-dollar reservation agreements well in advance of delivery, the same kind of take-or-pay style commitment covered above, and their combined 2026 AI infrastructure spending is projected in the neighborhood of 650 to 725 billion dollars across the 4 companies, according to multiple analyst compilations of the companies' own capital expenditure guidance. That scale of forward commitment is why a startup ordering the same generation of chip can face a materially longer wait than a hyperscaler ordering the same part.
Smaller AI labs and startups have responded by working around direct allocation entirely. A growing share of AI compute now runs through neocloud providers, companies that rent out GPU capacity by the hour rather than sell chips outright, specifically because these buyers cannot secure direct allocation from Nvidia at any price that makes sense for their scale. That rental market has its own price swings tied to the same underlying scarcity: spot pricing for older-generation chips has run well above blended reservation rates during periods of tight supply.
There is also a persistent enforcement problem that gets far less attention than product launches. Despite export controls, reporting over the past 2 years has documented Nvidia chips reaching China through third-country resellers and shell distributors, a gap that neither Washington nor Nvidia has fully closed. This changes who can actually get a chip, on what timeline, and at what contract size, the more practical question for most companies evaluating AI infrastructure in 2026.
The other shortage no chip headline mentions: grid power
Every allocation deal covered above assumes a company that wins a chip order can plug it in right away. In much of the United States right now, that assumption does not hold. The binding constraint on a new AI data center is increasingly the wait to connect to the power grid.
Lawrence Berkeley National Laboratory's interconnection research puts the median wait from initial application to commercial operation at nearly 5 years as of 2024, up from under 2 years in 2008, with roughly 2,300 gigawatts of generation and storage capacity currently stuck in queues nationwide, more than the country's entire installed capacity. Some regions run far worse than that median. Virginia's data center corridor, the densest concentration of data centers in the country, has interconnection queues stretching to 2032, inside a broader PJM queue holding 220 gigawatts of reformed applications. Dominion Energy has reported an average wait of 7 years for a 100 megawatt connection, and Wood Mackenzie's analysis found that nearly half of the US data centers scheduled for completion in 2026 now face delay or outright cancellation over permitting and grid shortfalls.
Developers have responded by building around the grid instead of waiting for it. Behind-the-meter natural gas generation has become the standard bridge in queue-heavy regions, and land banking activity in areas like West Texas has picked up specifically because of local gas availability. A 350-megawatt deployment of gas turbines runs about 500 million dollars in capital, according to industry reporting, and converts a multi-year utility wait into a build timeline measured in months rather than years.
This flips the usual framing of the chip race. A company with a smaller Nvidia allocation but an existing grid connection, or a behind-the-meter power deal already in place, can bring compute online faster than a company holding a bigger chip order and no path to power. The constraint has also become political rather than purely technical: Maine became the first state to ban new data center construction outright, in April 2026, a sign that grid pressure from AI buildouts is now a local policy fight, not just an engineering schedule. Winning the chip war and being able to actually run that hardware in 2026 have become 2 separate contests, and they are not always won by the same company.
The power problem that starts only after the grid connection is approved
A grid connection solves one bottleneck and immediately exposes a second one that gets almost no coverage: whether the building behind that connection can actually deliver enough power and cooling to a single rack. This is the part of the power story that even readers who already understand the interconnection queue problem above usually have not seen laid out.
Rack power density has climbed fast enough to strand facilities that were considered modern only a few years ago. Average rack density moved from roughly 16 kilowatts in 2025 to about 27 kilowatts in 2026, and the newest Nvidia GB300 NVL72 systems can draw over 140 kilowatts in a single rack, according to Schneider Electric's data center planning research. The current-generation GB200 NVL72 already pulls 120 to 130 kilowatts under full load, according to Network World's coverage of the shift toward liquid cooling. For comparison, facilities built even in the cloud-computing era of the 2010s were typically designed for 8 to 15 kilowatts per rack, and the industry-average rack still sits closer to 7.6 kilowatts, according to Uptime Institute figures cited in industry infrastructure analysis. A building can hold a fully approved, fully contracted grid connection and still be physically unable to route that power to enough racks at the density the newest chips require.
The fix is not simple or cheap. Rear-door heat exchangers, which replace a rack's rear door with a chilled-water coil assembly, are the most retrofit-friendly option and can handle 20 to 40 kilowatts per rack without a full facility rebuild, according to industry cooling analysis. Above roughly 80 kilowatts per rack, the GB200 NVL72 class, direct-to-chip liquid cooling becomes necessary, and that step usually means new power distribution, new cooling plumbing and reinforced flooring, closer to reconstruction than a retrofit. Capital costs for a full liquid-cooling buildout in an existing facility have been estimated in the 2 to 5 million dollar range per deployment in industry cost breakdowns, and operators who install liquid cooling for workloads that did not actually need it have reported paying roughly 40 times more than an optimized air-cooling upgrade would have cost for the same thermal outcome.
What this creates in practice: a 2-tier data center market. Newer, purpose-built facilities designed from the start for high-density, liquid-cooled racks can run the latest Nvidia and Huawei systems at full density. Older facilities, even ones with a live, approved grid connection, are increasingly being repositioned for lower-density inference workloads instead of training, because retrofitting them to frontier-training density costs more and takes longer than most operators are willing to commit to. Stranded capacity, contracted megawatts sitting unused because the building cannot route them to enough racks, is becoming its own quiet inefficiency inside the power story, separate from the interconnection queue that gets most of the attention.
The AI chip claims that fall apart under a fact check
A lot of AI chip coverage repeats the same lines without checking whether they still hold up. Here is where several of the most common ones land once checked against the reporting above.
| The claim | What the record shows |
|---|---|
| Higher peak TFLOPS means a faster chip in practice | Real throughput depends on memory bandwidth, interconnect speed and software maturity as much as raw compute, as the MFU gap between advertised and achieved performance shows |
| US export controls have stopped China's AI chip progress | They redirected demand toward domestic suppliers like Huawei, Cambricon and Moore Threads, effectively creating guaranteed customers those firms might not have had in an open market |
| Huawei's Ascend chips now match Nvidia's best hardware | Ascend is competitive for inference on already trained models. DeepSeek's own R2 training attempt shows frontier-scale training is a different, unresolved problem for Huawei |
| Intel's Crescent Island proves Intel is back in the AI chip race | As of mid-2026, Crescent Island has not shipped to a single paying customer. Sampling and shipping are 2 different milestones, and general availability is not expected until 2027 |
| The H200 approval means Nvidia's China business is recovering | Even the newest approval reporting suggests a cap below 200,000 units, less than half of what was requested, with actual deliveries still unresolved as of this update |
| More chips always means a better model | DeepSeek's own history shows algorithmic efficiency can narrow the gap with far less compute, so raw chip volume is one input among several, not a guaranteed outcome |
| China is years behind the US on AI chips across the board | China trails on frontier training but is roughly at parity on inference deployment, so the real gap is narrower in one job than in the other, not uniform across every workload |
The pattern across all 7 is the same one you see in other corners of tech reporting too, from oversold 5G coverage maps to the kind of router and ISP marketing claims that don't survive a technical read: a headline can be accurate and still misleading once the deployment reality gets checked.
What this actually means if you are not a chip investor
Most people reading AI chip news are not buying Nvidia stock or reading Huawei's quarterly filings for fun. Here is the plain version of why any of this matters to a regular business or user.
AI chip supply affects what AI tools cost and how fast new features roll out. When training chips are scarce or expensive, cloud AI subscriptions cost more, and smaller companies get squeezed out of building their own models. When inference chips get cheaper, as Intel and others are betting they will, running AI features inside everyday apps gets cheaper too, which usually shows up as lower prices or more free tier access for users, including the kind of AI tools people use for everyday tasks like budgeting and personal finance planning.
The China split matters even if you never touch a Chinese AI product. Two separate hardware and software ecosystems, one built on Nvidia and CUDA, one built on Huawei and its own tools, mean AI models trained on each stack behave a little differently. Developers building global products increasingly have to think about which stack their user base runs on, especially if they operate in or sell into China.
The export control back and forth is not just a headline, either. Every time Washington tightens or loosens the rules, it changes what Nvidia can sell, which changes Nvidia's revenue guidance, which moves markets that touch retirement accounts and index funds well beyond anyone who follows semiconductors specifically.
There is also a power, water and jobs angle that gets less attention than the chip specs themselves. Training and running these chips at scale requires enormous data center capacity, and the electricity demands behind that buildout are covered above in more technical detail than most coverage attempts. The water side of that same buildout is its own growing story worth understanding on its own terms. Some of the newest US data center projects have leaned on green building standards to manage that footprint, a path similar to what facilities elsewhere have already tested with mixed results. Meanwhile, Intel's 18A process runs through fabs in Arizona and Oregon, and Intel has framed its foundry push as a bet on rebuilding advanced chip manufacturing inside the US. Whether that succeeds depends on outside customers actually trusting Intel to build their chips, not just Intel's own products. Every Panther Lake laptop that ships without a defect and every Clearwater Forest server that hits its performance target is effectively a sales pitch to companies deciding right now whether to hand Intel their own chip designs to manufacture.
What to watch in AI chip news for the rest of 2026
A few concrete things will tell us more than any prediction can. Watch whether Nvidia's H200 chips actually ship to China in meaningful volume, not just get approved on paper, given that even this month's reporting still points to a capped, unresolved outcome. Watch Huawei's Ascend 950DT launch, expected in the fourth quarter, since it targets training and decoding workloads with 144 GB of HBM memory and a 2 terabyte per second interconnect, a step toward the training capability Huawei still lacks. Watch Intel's Crescent Island sampling results in the second half of the year, since that is the first real test of whether Intel's cheaper memory bet works in practice rather than on a spec sheet. Watch whether China's CXMT can actually scale HBM output past its current 2 million stack ceiling, since that single number may decide how many more Ascend chips Huawei can build once its stockpiled foreign memory runs out. Watch whether SMIC's 910C yield keeps closing in on the 60 percent industry standard Huawei is reportedly targeting, since every percentage point there is worth more real chips than any single new production announcement. And watch how many hyperscalers announce liquid-cooling retrofits versus new purpose-built facilities, since that ratio is a direct signal of how much stranded, undeliverable power capacity is sitting inside the industry right now.
Keep an eye on the policy and infrastructure side just as closely as the product side. In this market, a signature in Washington or Beijing, or a permit approval at a state utility commission, can move more revenue in a single afternoon than a new chip launch does in a year.
Quick answers on the AI chip race
Is Huawei catching up to Nvidia in 2026?
On inference, yes, close enough that China has decided it is good enough for now. On frontier training, no. DeepSeek's own attempt to train its R2 model on Ascend hardware ran into instability and had to switch back to Nvidia chips.
Why is there still an AI chip shortage in 2026?
HBM memory and TSMC's CoWoS packaging capacity are sold out into 2027, wafer supply is locked up years ahead through prepaid take-or-pay contracts, and grid interconnection queues can delay a data center by years. The bottleneck sits in the supporting supply chain, not in any single chip design.
Can Nvidia's H200 chip legally reach China right now?
Approvals have moved forward in stages through 2026, but reporting as of July 2026 points to a capped volume below 200,000 units, less than half of what Chinese buyers reportedly requested, with actual deliveries still unresolved.
Does mixing old and new GPU generations in one cluster save money?
Usually not for synchronous training. A real test mixing Nvidia B200 and A100 GPUs in one training job found the older chips ran about 30 percent slower and the newer chips sat idle roughly 30 percent of the time, which erased most of the expected speed gain.
USA Beam take
The AI chip race in 2026 splits Nvidia's performance lead against Huawei's speed of scale and Intel's bet on cheaper inference, all inside a US-China policy fight that none of the 3 companies control. Underneath all 3 sit constraints none of them fully control either: HBM memory and TSMC packaging capacity sold out for years, wafer supply locked in years ahead through prepaid contracts that favor whoever has the most leverage, a yield gap that turns Huawei's production targets into a ceiling rather than a promise, cluster designs that can quietly erase a newer chip's advantage if mixed with older hardware, and a grid and rack power problem that can delay a fully funded, fully allocated data center by half a decade regardless of whose chips sit inside it.
Nvidia still makes the best single chip on the market by a wide margin, and its revenue numbers show customers lining up despite losing almost all of its China business. Huawei has not closed the technical gap in training, as DeepSeek's own Ascend experience shows, and the fault-recovery software behind that gap is a fixable problem rather than a permanent one. Huawei has closed the gap that matters most for its current market, inference, and that segment is growing the fastest inside China. Intel has real funding and a real product timeline for the first time in years, though nothing it has shown has shipped to a paying customer yet.
The facts point to a market splitting into 2 tracks rather than one company winning outright, constrained on every side by how much memory, packaging, yield, contract capacity and power actually exists this year. That structural reality is probably a bigger story than any single chip release in 2026.
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Editor's note: All images accompanying this article were created using AI image generation. All data, figures and case studies in the article itself are drawn from cited public sources.
